Methods and Apparatus for Designing and Constructing Dual Write Memory Circuits with Voltage Assist

ABSTRACT

Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the V DD  power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

TECHNICAL FIELD

The present invention relates to the field of digital memory circuits.In particular, but not by way of limitation, the present inventiondiscloses techniques for designing and constructing multi-port memorycircuits using a voltage assist.

BACKGROUND

Most digital memory circuits are “single port” memory devices that canonly be read from or written to by a single user at a time. For example,the well-known standard six-transistor (6T) SRAM bit cell only has asingle port into the bit cell for reading or writing data bit values.However, for many applications it is desirable to have “multi-port”memory systems where more than one memory user can read from singlememory cell at the same time. For example, in a multi-core processorsystem it is advantageous to allow multiple cores to read from the samememory address concurrently.

To allow for more than one memory reader to concurrently access a singlememory bit cell, the circuit design of the memory bit cell may bealtered to include more physical ports into the memory bit cell. Forexample, the standard single-port 6T SRAM bit cell may be made into adual-port memory cell by inserting two additional transistors into thememory bit cell circuit that implement a second physical port foraccessing the data bit stored in the memory bit cell. Such dual-port 8TSRAM bit cells are often used when a digital system needs the ability toperform two concurrent memory accesses.

Adding two additional transistors into a memory cell allows for twoconcurrent readers of the memory cell but reduces other importantmetrics of the memory bit cell. Specifically, inserting two additionaltransistors increases the size of the memory bit cell and thus reducesthe memory density of an array created from the 8T SRAM cells.Furthermore, due to the risk of losing the value of the data bitcurrently stored in the SRAM bit cell if two concurrent read operationsare received, certain transistors in the dual-port 8T SRAM bit cell mustbe made much larger thus further increasing the size of the dual-port 8TSRAM bit cell and reducing memory density. Adding additional ports (suchas a third or fourth port) by adding even more transistors furthercompounds these problems. Thus, as a result, multi-port memory bit cellstend to have very low memory density metrics. The additional transistorswill also require additional power to operate such that multi-portmemory systems will also consume more power than single port memorysystems. Therefore, it would be desirable to have alternative circuitdesigns for implementing multi-port memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsdescribe substantially similar components throughout the several views.Like numerals having different letter suffixes represent differentinstances of substantially similar components. The drawings illustrategenerally, by way of example, but not by way of limitation, variousembodiments discussed in the present document.

FIG. 1 illustrates a computer system within which a set of instructions,for causing the machine to perform any one or more of the methodologiesdiscussed herein, may be executed.

FIG. 2A illustrates a typical six transistor (6T) SRAM bit cell.

FIG. 2B illustrates the process of writing a logical one into the 6TSRAM bit cell of FIG. 2A.

FIG. 2C illustrates a full transistor view of the 6T SRAM bit cell fromFIG. 2A.

FIG. 3A illustrates a difficult situation encountered when reading thedata bit stored in a typical 6T SRAM bit cell.

FIG. 3B illustrates how the difficult situation of FIG. 3A is handledwith an inverter transistor that is larger than the port transistor.

FIG. 4 illustrates a transfer function for a typical inverter circuit.

FIG. 5A illustrates a typical dual-port eight transistor (8T) SRAM bitcell.

FIG. 5B illustrates a difficult situation that may occur when readingfrom a dual-port 8T SRAM bit cell of FIG. 5A.

FIG. 6A illustrates a proposed dual-port six transistor (6T) SRAM bitcell.

FIG. 6B illustrates a block diagram of a memory array constructed withthe dual-port 6T SRAM bit cell of FIG. 6A.

FIG. 6C illustrates a block diagram of the dual-port 6T SRAM bit cell ofFIG. 6A coupled to sense amplifiers for performing pseudo differentialread operations.

FIG. 6D illustrates a block diagram of a memory array constructed withthe dual-port 6T SRAM bit cell of FIG. 6A that has sense amplifierslocated in the center of the array.

FIG. 7 illustrates a timing diagram for a memory system that performseither one write (1W) operation per cycle or two read (2R) operationsper cycle.

FIG. 8A illustrates a split word line 6T SRAM bit cell receiving asingle-ended write operation of a logical “1” data bit.

FIG. 8B illustrates the split word line 6T SRAM bit cell of FIG. 8Achanging state in response to the write operation of a logical “1” databit.

FIG. 8C illustrates a final state of the split word line 6T SRAM bitcell of FIG. 8B after the word line has been deactivated upon completingthe write operation.

FIG. 9A illustrates a timing diagram of two concurrent write operationsperformed in a single cycle by lowering the V_(DD) power voltage toenable single-ended writes.

FIG. 9B illustrates a timing diagram for a memory system with a reducedoperating V_(DD) power voltage that handles two concurrent readoperations by raising the V_(DD) power voltage provided to the rowsbeing read.

FIG. 10 illustrates a high-level layout diagram of a subsection of splitword line memory cells within a memory array.

FIG. 11 illustrates a block diagram of a memory system that includes awrite buffer such that the memory system can handle a concurrent writeoperation and read operation (1W and 1R) in a single cycle.

FIG. 12A illustrates a flow diagram that describes how the memory systemof FIG. 11 may handle two concurrent write operations or two concurrentread operations.

FIG. 12B illustrates a flow diagram that describes how the memory systemof FIG. 11 may handle concurrent read and write operations withoutconcurrently accessing the same row of a memory array.

FIG. 13 illustrates a dual-port memory system that uses a write bufferto improve the performance of the memory system.

FIG. 14 illustrates a flow diagram that describes how the memory systemof FIG. 13 may be improved by preventing reads and writes fromconcurrently accessing the same row in a memory array.

DETAILED DESCRIPTION

The following detailed description includes references to theaccompanying drawings, which form a part of the detailed description.The drawings show illustrations in accordance with example embodiments.These embodiments, which are also referred to herein as “examples,” aredescribed in enough detail to enable those skilled in the art topractice the invention. It will be apparent to one skilled in the artthat specific details in the example embodiments are not required inorder to practice the present invention. For example, although some ofthe example embodiments are disclosed with reference to computerprocessing systems used for packet-switched networks, the teachings canbe used in many other environments. Thus, any digital system that usesdigital memory can benefit from the teachings of the present disclosure.The example embodiments may be combined, other embodiments may beutilized, or structural, logical and electrical changes may be madewithout departing from the scope of what is claimed. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope is defined by the appended claims and their equivalents.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one. In this document, the term“or” is used to refer to a nonexclusive or, such that “A or B” includes“A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.Furthermore, all publications, patents, and patent documents referred toin this document are incorporated by reference herein in their entirety,as though individually incorporated by reference. In the event ofinconsistent usages between this document and those documents soincorporated by reference, the usage in the incorporated reference(s)should be considered supplementary to that of this document; forirreconcilable inconsistencies, the usage in this document controls.

Computer Systems

The present disclosure concerns digital memory devices that are oftenused in computer systems. FIG. 1 illustrates a diagrammaticrepresentation of a machine in the example form of a computer system 100that may be used to implement portions of the present disclosure. Withincomputer system 100 of FIG. 1, there are a set of instructions 124 thatmay be executed for causing the machine to perform any one or more ofthe methodologies discussed within this document. Furthermore, whileonly a single computer is illustrated, the term “computer” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 100 of FIG. 1 includes a processor 102(e.g., a central processing unit (CPU), a graphics processing unit (GPU)or both) and a main memory 104 and a static memory 106, whichcommunicate with each other via a bus 108. The computer system 100 mayfurther include a video display adapter 110 that drives a video displaysystem 115 such as a Liquid Crystal Display (LCD). The computer system100 also includes an alphanumeric input device 112 (e.g., a keyboard), acursor control device 114 (e.g., a mouse or trackball), a disk driveunit 116, a signal generation device 118 (e.g., a speaker) and a networkinterface device 120. Note that not all of these parts illustrated inFIG. 1 will be present in all embodiments. For example, a computerserver system may not have a video display adapter 110 or video displaysystem 115 if that server is controlled through the network interfacedevice 120.

The disk drive unit 116 includes a machine-readable medium 122 on whichis stored one or more sets of computer instructions and data structures(e.g., instructions 124 also known as ‘software’) embodying or utilizedby any one or more of the methodologies or functions described herein.The instructions 124 may also reside, completely or at least partially,within the main memory 104 and/or within a cache memory 103 associatedwith the processor 102. The main memory 104 and the cache memory 103associated with the processor 102 also constitute machine-readablemedia.

The instructions 124 may further be transmitted or received over acomputer network 126 via the network interface device 120. Suchtransmissions may occur utilizing any one of a number of well-knowntransfer protocols such as the well-known File Transport Protocol (FTP).While the machine-readable medium 122 is shown in an example embodimentto be a single medium, the term “machine-readable medium” should betaken to include a single medium or multiple media (e.g., a centralizedor distributed database, and/or associated caches and servers) thatstore the one or more sets of instructions. The term “machine-readablemedium” shall also be taken to include any medium that is capable ofstoring, encoding or carrying a set of instructions for execution by themachine and that cause the machine to perform any one or more of themethodologies described herein, or that is capable of storing, encodingor carrying data structures utilized by or associated with such a set ofinstructions. The term “machine-readable medium” shall accordingly betaken to include, but not be limited to, solid-state memories, opticalmedia, and magnetic media.

For the purposes of this specification, the term “module” includes anidentifiable portion of code, computational or executable instructions,data, or computational object to achieve a particular function,operation, processing, or procedure. A module need not be implemented insoftware; a module may be implemented in software, hardware/circuitry,or a combination of software and hardware.

Static Random Access Memory (SRAM) Overview

A static random access memory (SRAM) is a type of semiconductor memorycircuit that stores each data bit in a simple memory cell circuit thatoften consists of a pair of connected inverters. FIG. 2A illustrates atypical SRAM cell comprising a pair of inverters 241 and 242. Theinverters 241 and 242 are typically connected in a loop circuit whereinthe output of each inverter is coupled to the input of the otherinverter. One side of the memory cell circuit is referred to as the dataor “true” side 291 that stores the data bit value and the other side ofthe memory cell circuit is referred to as the data-complement or “false”side 291 that stores the logical inverse of the stored data bit.

To write a data bit into a memory cell or read a data bit from thememory cell, there are a pair of port transistors 231 and 232 that arecoupled to a common word line 210. The port transistors 231 and 232receive data from (for write operations) or drive data onto (for readoperations) a complementary pair of data bit lines: bit line (BL) 220and bit line complement 225. FIG. 2B illustrates writing a “1” data bit(generally represented by a positive voltage value) into the data (or“true”) side 291 and “0” data bit (generally represented by ground) intothe data-complement (or “false”) side 292 of the memory cell throughport transistors 231 and 232, respectively.

FIG. 2C illustrates the SRAM cell FIG. 2A with the inverter symbolsreplaced with a set of four transistors used to implement the twoinverter circuits 241 and 242. Each inverter circuit is implemented withtwo transistors: a PMOS transistor and a NMOS transistor. Since thereare two transistors for each of the two inverter circuits and there aretwo transistors (231 and 232) used for ports into the memory cell, theSRAM cell of FIGS. 2A to 2C is commonly known as a six-transistor (6T)SRAM bit cell.

The physical geometry of the integrated circuit components used toconstruct a 6T SRAM cell is very important in order to guarantee properoperation of the 6T SRAM cell. For example, if the NMOS transistor inthe inverter is the same physical size as the NMOS transistor used as aport transistor into the 6T SRAM bit cell then the 6T SRAM bit cell mayunintentionally lose store data during read operations. An illustrationas to why the physical geometry is so important is set forth withreference to FIG. 3A.

FIG. 3A illustrates an example of a 6T SRAM bit cell that currentlystores a “0” data bit (on ‘true’ side 308 of the bit cell) that is beingread from the 6T SRAM cell. The ‘false’ side 309 of the 6T SRAM cellstores a “1” bit that activates inverter NMOS transistor 344 such thatNMOS transistor 344 is turned on. Similarly, the driving the word line310 for the read operation activates port NMOS transistor 331 such thatport transistor 31 is turned on. Thus, during a read of a 6T SRAM cellstoring a “0” data bit, there is an electrical path from bit line 320 tothe ground after inverter NMOS transistor 344. To simplify the analysisin this example, these two turned-on NMOS transistors (344 and 331) actsimilar to a pair resistors in series for time period during the actualread operation.

Before a reading a memory cell in a memory array, the memory system readcircuitry generally pre-charges the bit line 320 for the read operation.Assuming port NMOS transistor 331 and inverter NMOS transistor 344 arecreated approximately the same size, the two NMOS transistors (344 and331) may be assigned a resistance value of R Ohms. Thus, when thepre-charged voltage value on the bit line 320 accesses the data side atpoint V_(L) 308 in the memory cell, port NMOS transistor 331 andinverter NMOS transistor 344 initially act as a voltage divider circuitthat drives the voltage at point V_(L) 308 to middle voltage level(between the pre-charge voltage and ground) since the two transistorshave approximately the same resistance R Ohms. With the voltage at pointV_(L) 308 driven to middle voltage level, that middle voltage level mayaccidentally cause the data value state currently stored in the memorycell to flip.

Driving point V_(L) 308 to middle voltage level (due to the pre-charge)may flip the data state of the memory bit cell since the invertercircuit 341 may be unintentionally triggered. FIG. 4 illustrates aninverter circuit transfer function. When the input to an invertercircuit is in the low region 431 the output is high and when the inputto an inverter circuit is in the high region 433 the output will be low.However, when an input voltage in the middle region 432, the output maybe high, low, or in the middle depending on the input voltage and thespecific inverter circuit. Specifically, due to manufacturingdifferences, the transfer function illustrated in FIG. 4 may be shiftedto the left or right such that the output voltage will vary depending onthe specific inverter geometry, doping, etc. Referring back to FIG. 3A,if the middle voltage value at point V_(L) 308 is interpreted as highvalue then the inverter 341 (driven by the voltage at point V_(L) 308)may be activated unintentionally flip the data value stored in thememory cell during the read operation.

The simplified example set forth in the preceding paragraphs illustrateshow the pre-charge at the start of a read operation may accidentallydestroy the data stored in a 6T SRAM cell. To prevent this from everoccurring, the size ratio of the inverter NMOS transistor 344 and theport NMOS transistor 331 must be carefully considered. Specifically, toprevent having read operations unintentionally flip the data valuestored in the memory cell during a read operation, the inverter NMOStransistor 344 is generally made larger than the port NMOS transistor331 such that inverter NMOS transistor 344 will more easily carrycurrent when activated. Thus, when both of these two NMOS transistorsare active (turned-on), the inverter NMOS transistor 344 will have amuch lower resistance than the port NMOS transistor 331. An illustrativeexample is presented in FIG. 3B where inverter NMOS transistor 344 has aresistance R and port NMOS transistor 331 has twice the resistance witha resistance value of 2R. When the same read situation occurs, thevoltage divider circuit will now have a much smaller voltage drop acrossinverter NMOS transistor 344 such that the voltage at point V_(L) 308will remain low despite the pre-charge thus ensuring that the 6T SRAMcell will retain the stored data bit value.

The physical size ratio of the inverter NMOS transistor 344 and the portNMOS transistor 331 is the important factor. If size ratio (inverterNMOS transistor 344)/(port NMOS transistor 331) is not large enough thenthe voltage at node V_(L) 308 may reach the threshold voltage thatactivates inverter 341 thus causing the memory cell to invert the storeddata value during the read operation. The higher the (inverter NMOStransistor 344)/(port NMOS transistor 331) size ratio is the lower thevoltage at node V_(L) 308 will be during the pre-charge. But to keep thememory cell as small as possible, the ratio should only be as high asnecessary to prevent data corruption. In many 6T SRAM cells, the sizeratio is 1.2 to 1.5.

8T Dual-Port SRAM Bit Cell

In many memory applications, it is desirable to allow two differententities to access the same memory system concurrently. Occasionally,the two different entities may attempt to access the very same SRAM bitcell at the same time. For example, in a multi-core processor systemmore than one of the different processing cores may attempt to accessthe same memory cell at the same time. To allow for such concurrentmemory accesses, a second physical port into a memory cell may be addedto the memory cell circuitry.

FIG. 5A illustrates an example of a typical dual-port SRAM cell that canhandle two completely independent but concurrent memory accesses. Thedual-port SRAM cell of FIG. 5A is similar to the 6T SRAM cell of FIG. 2Aexcept that in addition to the first pair of complementary porttransistors 531 and 532, the dual-port memory cell of FIG. 5A alsoincludes a second pair of complementary port transistors 533 and 534.The second pair of complementary port NMOS transistors 533 and 534 arecontrolled by second word line (word line B) 511. Similarly, the secondpair of complementary port transistors 533 and 534 also have their ownrespective bit lines (data bit line B 521 and data bit line B complement526). Since two more transistors were added to the memory cell circuit,the memory circuit of FIG. 5A is typically referred to as a dual-port 8TSRAM cell.

The addition of a second set of complementary port transistors (533 and534), a second set of complementary bit lines (521 and 526), and anadditional word line (511) allows two different entities to concurrentlyaccess the contents of the 8T SRAM cell independently of each other.However, this ability to concurrently access the SRAM cell using the twoindependent ports comes at a cost of significantly increasing thephysical size of the SRAM cell due to the additional area required toaccommodate the additional complementary port transistors (533 and 534),the additional complementary bit lines (521 and 526), and the additionalword line (511).

In addition to the added memory cell elements, the NMOS transistors usedto implement the inverters within SRAM cell may need to be made evenlarger to prevent the loss of data during a read operation. For example,FIG. 5B illustrates a circuit diagram of half of a dual-port 8T SRAMcell wherein two entities are attempting to read the SRAM cell byaccessing both ports into the SRAM cell simultaneously. If all of theNMOS transistors are the same size and both lines pre-charged then thevoltage at data node V_(L) 508 of the memory cell may be driven to 0.6times the pre-charge voltage level. Thus, this concurrent read scenariopresents a significant risk of unintentionally changing the data valuein the memory cell during a read operation. To prevent this significantrisk of changing the stored data bit value, inverter NMOS transistor 544is typically designed to be significantly larger than the port NMOStransistors 531 and 533 to reduce the resistance across invertertransistor 544 thereby reducing the voltage at data node V_(L) 508. Thetransistor size ratio is the key statistic used.

Note that the transistor size ratio of (inverter NMOS transistor544)/(port transistors 531 or 533) must continue to grow with the numberof additional ports added to the SRAM cell. Thus, in the dual-port 8TSRAM cell of FIG. 5A the inverter NMOS transistor 544 must be largerthan the inverter NMOS transistor 344 in the single port SRAM cell ofFIG. 3A. Similarly, with a three-port 10T SRAM cell (not shown), theinverter transistor will be even larger than the inverter transistor 544in the dual-port 8T SRAM cell of FIG. 5A. The inverter transistor sizemay grow proportionally. For example, if the transistors size ratio usedin a single port 6T SRAM cell of is (inverter transistor 344)/(porttransistor 231) is selected to be 1.5 then in the dual-port 8T SRAM cellthe ratio may be (1.5*2)=3 and in a three-port 10T SRAM cell the ratiomay be (1.5*3)=4.5. This ratio continues to grow thus making SRAM cellswith larger numbers of ports very large and cumbersome.

Due the additional circuit elements needed (bit lines, port transistors,and a word line) and the need for a larger NMOS transistor in theinverter, the dual-port 8T SRAM cell of FIG. 5A is typicallysignificantly larger than the 6T SRAM cell of FIG. 2A. Thus, the memorydensity (memory data bits per unit area) for a memory system made up ofan array of dual-port 8T SRAM cells will be significantly lower than thememory density of memory system made up of an array of single-port 6TSRAM cells. It would therefore be desirable to find other ways ofdesigning dual-port SRAM bit cells.

2 Reads with 6T Dual-Port SRAM with Split Word Line

Referring back to FIG. 2A, the basic 6T SRAM cell has two porttransistors 231 and 232 with two associated complementary bit lines 220and 225. There are two main reasons that two complementary bit lines areused within the standard 6T SRAM cell: (1) the ability to effectivelyand reliably write data into the memory cell; and (2) read access speed.

The critical reason for having two complementary bit lines is that it isvery difficult if not impossible to write a “1” data value into astandard 6T SRAM bit cell from only one side of the 6T SRAM cell. Recallthat in FIG. 3B the inverter NMOS transistor 344 was constructed muchlarger than the port NMOS transistor 331 in order to prevent thepre-charge voltage of a read operation from destroying a stored “0” datavalue when a read operation is performed. For the very same reason thatthe larger inverter NMOS transistor 344 was needed, that larger inverterNMOS transistor 344 makes it difficult to write a logical “1” value tothe memory bit cell. Specifically, the positive voltage (˜1V in theexample of FIG. 3B) placed onto bit line 320 when writing a logical “1”passes through port NMOS transistor 331 and inverter NMOS transistor 344that together act as a voltage divider. Since inverter NMOS transistor344 is much larger than port NMOS transistor 331 (and thus has lowerresistance), the voltage at point V_(L) 308 will often not be highenough to effectively write a logical “1” into the memory cell.

In order to effectively and reliably write a new logical “1” data valueinto a standard 6T SRAM cell, the complementary bit line 325 isgenerally required. Referring back to FIG. 3B, if a positive voltage(logical “1”) is placed on bit line 320 during a write operation then acomplementary zero voltage value (logical “0”) will be placed on thecomplementary bit line 325 during the write operation. The zero voltage(logical “0”) on the complementary bit line 325 will propagate throughport transistor 332 to cause a zero voltage value at point V_(R) 309that controls PMOS transistor 343 and NMOS transistor 344. The zerovoltage value at point V_(R) 309 turns on PMOS transistor 343 and turnsoff NMOS transistor 344 thus increasing the voltage at point V_(L) 308to V_(DD) thereby writing a logical “1” into the memory cell. Thus, thewriting of a logical “0” into one side of a memory bit cell causes theother side of the memory bit cell to become a logical “1” using theinverter of the memory bit cell.

The net effect of this phenomenon is that with a standard 6T SRAM bitcell, only a logical “0” can be written into the memory bit cell.However, since there is both a data/true side of a memory bit cell and adata-complement/false side of the memory cell, a logical “1” may bewritten into the memory bit cell by writing a logical “0” into thedata-complement/false side of the memory bit cell that will cause theinverter to drive data/true side of the memory cell to become a logical“1”.

As noted above, read access speed is a second reason that complementarybit lines are used in a standard 6T SRAM cell. It is possible to readthe data state of a memory bit cell by reading from only one side of thememory bit cell. For example, referring to FIG. 3A, a memory readingcircuit could turn on word line 310 and only sample the data/true sideof the standard 6T SRAM cell to obtain the stored data bit. However, byaccessing both sides (308 and 309) of the memory cell concurrently, adifferential amplifier coupled to the pair of complementary bit lines(320 and 325) can read the state of the memory bit cell faster than byreading from a single end of the memory cell. Thus, traditional 6T SRAMcells generally perform read operations by simultaneously reading fromboth sides (308 and 309) of the SRAM bit cell.

If an integrated circuit designer is willing to accept a slower readoperation speed for a particular application, then the traditional 6TSRAM cell may be modified to create a one write port or two read portSRAM bit cell. FIG. 6A illustrates one embodiment of a one write port ortwo read port (1W or 2R) 6T SRAM bit cell. In the 1W or 2R memory cellof FIG. 6A, there are two independently controllable word lines (wordline X 610 and word line Y 615) that each control associated porttransistors (631 and 632) located on opposite sides of the memory cell.FIG. 6B illustrates a high level block diagram of a memory arraycontaining an array of the split-word line 1W or 2R memory cells of FIG.6A. Not that each row of the memory array has both an X word line and Yword line that each independently control one of the two bit lines.

Write operations into the 1W or 2R memory cell of FIG. 6A may be handledin the same manner as a traditional 6T SRAM cell. Specifically, toperform a write operation, the write circuitry (not shown) asserts bothword line X 610 and word line Y 615 simultaneously for the same row tosimultaneously activate the both port transistors 631 and 632,respectively. The write circuitry also drives bit line X 620 and bitline Y 625 as traditional complementary data bit lines where bit line X620 asserts the data bit and bit line Y 625 asserts the complement ofthe data bit. FIG. 7 illustrates a timing diagram with middle portionillustrating a single write per clock cycle being performed.

To perform two concurrent read operations into the 1W or 2R memory cellof FIG. 6A, word line X 610 and word line Y 615 are operatedindependently for the two different concurrent read operations. Wordline X 610 is asserted in one row for a first read operation using bitline X 620 and word line Y 615 is asserted (in different row or the samerow of the same memory array) for a second concurrent read operationusing bit line Y 625 (in another column or the same column of thearray). Note that the read operation performed using word line Y 615 andbit line Y 625 will be read from the data-complement/false side of amemory cell such that the read data bit must be inverted for the truedata bit value. The bottom portion of FIG. 7 illustrates a timingdiagram of two concurrent read operations being handled in a singleclock cycle by concurrently using the two different word lines (andassociated bit lines) for the two independent read operations.

The physical construction of the 1W or 2R memory cell of FIG. 6A is verysimilar to the traditional single port 6T SRAM cell of FIG. 2C exceptthat the 1W or 2R memory cell of FIG. 6A requires two independent wordlines (word line X 610 and word line Y 615) routed to each SRAM cell.This can be managed by using the standard techniques for routing the twoword lines used in the dual-port 8T SRAM cell of FIG. 5A with thesmaller single port 6T SRAM cell of FIG. 2C. The resulting 1W or 2Rmemory cell of FIG. 6A will be significantly smaller than the dual-port8T SRAM cell of FIG. 5A since there is only one port transistor on eachside of the memory cell and there is no need to make the inverter NMOStransistor much larger to prevent a concurrent read operation fromaccidentally changing the state of the SRAM bit cell.

In one particular embodiment, the size of the inverter's PMOS transistor643 and the port transistor 631 are approximately the same size.However, the size of the inverter's NMOS transistor 644 is approximately1.5 times as large as the port NMOS transistor 631 in order to preventthe pre-charge phase of read operations from destroying stored data bitsas previously described with reference to FIGS. 3A and 3B.

The two concurrent but independent read operations performed with thememory system of FIGS. 6A and 6B use spatial division multiplexing (SDM)to accomplish the two independent concurrent read operations.Specifically, one area of the memory array space (word line X, bit lineX, and a left port transistor) is used for the first read operation anda second area of the memory array space (word line Y, bit line Y, andthe right port transistor) is used for the independent second readoperation.

Improved Concurrent Reads with 6T Dual-Port SRAM with Split Word Line

The split word line memory system of FIGS. 6A and 6B allows for eitherone write operation (1W) or two concurrent read operations (2R) duringeach memory cycle. However, the “single-ended” read operations will notbe as fast as normal differential read operations that require the useof two complementary bit lines. Specifically, the small SRAM bit celllacks the power to quickly drive a single ended data value. To improveupon this situation, a “pseudo” differential read operation may beperformed to increase the speed of a read operation.

FIG. 6C illustrates an arrangement for performing a pseudo differentialread operation. In FIG. 6C each bit line is coupled to a sense amplifierthat also has a synthetically generated voltage reference value as aninput. The synthetically generated voltage reference value is somewherebetween the voltage value for a logical “1” and the voltage value for alogical “0”. During a pseudo differential read operation, the output ofa bit line is compared against the synthetically generated referencevoltage value to output a data value faster than can be achieved withdirect single-ended read operation.

As illustrated in the embodiment of 6B, the sense amplifiers may besituated at the bottom of a memory array. However, this configurationrequires the memory cells to drive very long bit lines. Driving verylong bit lines reduces the performance of the memory system due to thecapacitance and resistance on the long data line. To improve upon thissituation, the sense amplifier circuits may be implemented in the middleof the memory array as illustrated in the embodiment of FIG. 6D. Thevoltage reference generator circuits used for pseudo differential readoperations may be placed at the edges of the memory array and providevoltage reference values along bit lines that are not being used. Notethat the complementary bit line does not need to be used, any free bitline may be used to carry the voltage reference as long as that voltagereference is properly directed to the sense amplifier.

Two Writes Per Cycle (2W) with a 6T Dual-Port SRAM Cell

The previous two sections described how the traditional 6T SRAM cell ofFIG. 6A may be modified with split word lines in order to implement amemory system that can handle two concurrent read operations in a singleoperating cycle. However, that split word line based memory system canstill only handle a single write operation during each operating cyclesince both bit lines (620 and 625) are required at the same time toperform a standard differential write operation.

The difficulty with write operations lies in the fact that it is verydifficult if not impossible to write a logical “1” into either side ofthe memory bit cell using only a single-ended write operation. To remedythe difficulty of writing a logical “1” into a bit cell, a logical “0”is concurrently written into the other side of the memory bit cell suchthat an inverter in the memory bit cell then helps writes the logical“1” into the other side of the memory bit cell. To provide fulldual-port memory functionality, it would be desirable to be able to reador write into a memory bit cell using only a single end of the memorybit cell.

Referring back to FIG. 3B, the difficulty in writing a logical “1” intoa memory bit cell originates from the fact that the NMOS transistor 344of the inverter in a memory cell is intentionally manufactured largerthan the port NMOS transistor 331 in order to reduce the voltage atpoint V_(L) 308 during the pre-charge phase of a read operation.Specifically, the larger NMOS transistor 344 has reduced resistance suchthat voltage drop across NMOS transistor 344 is smaller than the voltagedrop across the port NMOS transistor 331 thereby preventing thepre-charge voltage from unintentionally writing a logical “1” into thememory bit cell during a read operation. Unfortunately, the reducedresistance of the NMOS transistor 344 also reduces the voltage at pointV_(L) 308 when an actual write operation attempts to write a logical “1”into a single side of the memory bit cell such that the write operationwill fail unless there is a logical “0” concurrently written into theother side of the memory bit cell.

To remedy this situation that prevents single-ended writes of logical“1”s, it would be advantageous if the memory bit cell operated in adifferent manner during read operations and write operations.Specifically, the NMOS transistor 344 of the inverter should have a lowresistance value during read operations in order to prevent pre-chargesfrom over-writing stored data but the NMOS transistor 344 should have ahigher resistance value during write operations that would allow logical“1” values to be easily written into a single side of the memory bitcell. Specifically, a higher resistance values during write operationswould allow point V_(L) 308 to achieve a higher voltage value whenwriting a logical “1” into the memory bit cell. The higher voltage atpoint V_(L) 308 could then flip the other side of the memory cell to alogical “0” by using inverter 341 to flip the data value at point V_(R)309.

The NMOS transistor 344 in a memory bit cell is a field effecttransistor (FET) that has two main operating states: a linear region anda saturation (or active mode) region. In a digital circuit, thesaturation region is generally more important since that is where thecircuit operates when it is fully “turned on”. In the saturation regionof operation, the electrical current from drain to source (I_(D)) can bemodelled as:

$I_{D} = {\frac{\mu_{n}C_{ox}}{2}\frac{W}{L}\left( {V_{GS} - V_{T}} \right)^{2}}$

Where

μ_(n)=charge-carrier mobility (constant)

C_(ox)=gate oxide capacitance per unit area (constant)

W=gate width (constant)

L=gate length (constant)

V_(GS)=Gate to source voltage (variable)

V_(T)=Threshold Voltage for operation (constant)

In preceding equation, almost all of the terms are fixed constants for aparticular transistor once that transistor has been manufactured.However, one term in the equation that is not a fixed constant is thesquared term containing the variable gate-to-source V_(GS) voltagevalue. In fact the (V_(GS)−V_(T))² term of the equation dominates themodel due to the exponential component. Thus, if the gate to sourcevoltage of the transistor (V_(GS)) is reduced, the current from drain tosource (I_(D)) will also be reduced. Therefore, reducing the gate tosource voltage (V_(GS)) of the transistor effectively increases the“resistance” of the field effect transistor.

By controlling the gate to source voltage (V_(GS)) of the inverter NMOStransistor in a memory bit cell, a memory bit cell circuit can be madeto function differently during read operations than it functions duringwrite operations. Specifically, by lowering the gate to source voltage(V_(GS)) of the transistor and thereby increasing its resistance, thevoltage at the inverter NMOS transistor is increased such that asingle-ended write of a logical “1” may be successfully performed. Anillustration of a single-ended write of a logical “1” is set forth withreference to FIGS. 8A, 8B, and 8C.

FIGS. 8A, 8B, and 8C illustrate an example of how controlling thegate-to-source voltage (V_(GS)) of an inverter transistor in memory bitcell may facilitate a single-ended write of logical “1” into a 6T SRAMcell. Referring to FIG. 8A, a memory bit cell currently stores a logical“0” data bit since the data/true side has a logical “0” (represented byground) at point V_(L) 808 and the data-complement/false side has alogical “1” (represented by a small positive voltage value such as 1V)at point V_(R) 809. The logical “0” (ground) stored on the data/trueside at point V_(L) 808 activates the PMOS transistor 847 coupled toV_(DD) (and turns off NMOS transistor 848 coupled to ground) such thatthe voltage at the gate of NMOS transistor 844 is substantially equal tothe V_(DD) power voltage value as illustrated by signal pathway 888illustrated in FIG. 8A.

By lowering the voltage of V_(DD) value to a lower voltage value(V_(low)), the gate-to-source voltage (V_(GS)) of the inverter NMOStransistor 844 is reduced to V_(low) such that the resistance acrossinverter NMOS transistor 844 should be increased. For illustrationpurposes, the resistance depicted as a value of 2R Ohms relative to theresistance value of R Ohms across the port NMOS transistor 831 that isactivated with a normal activation voltage level. Note that an externalcircuit outside of the memory array provides the V_(DD) voltage suchthat the V_(DD) voltage can easily be controlled.

When a write operation of a logical “1” data bit is received while theV_(DD) power voltage value is held at the lower voltage value (V_(low))(as illustrated in FIG. 8A) then the memory cell circuit can handle asingle-ended write of the logical “1” data bit. Specifically, a logical“1” data bit (represented by ˜1 Volt in this example) is driven on bitline X 820 and the word line X 810 is asserted with a full normalvoltage value to turn on port NMOS transistor 831 into the memory bitcell. Note that the normal voltage value asserted on word line X 810 ishigher than the V₁₀ value such that the resistance across port NMOStransistor 831 will be lower than the resistance across resistanceacross inverter NMOS transistor 844.

Referring now to FIG. 8B, the logical “1” data bit asserted on bit lineX 820 passes through port NMOS transistor 831 (with a small voltagedrop) to the data/true side of the memory bit cell at point V_(L) 808.From point V_(L) 808, the logical “1” data value being written alsopasses through inverter NMOS transistor 844 to ground initially sincethe gate to source voltage (V_(GS)) of the inverter NMOS transistor 844is originally controlled by the logical “1” state that was stored atpoint V_(R) 809. However, since the V_(DD) power voltage is a lowvoltage value (V_(low)) the low gate-to-source voltage (V_(GS)) of theinverter NMOS transistor 844 causes the resistance of inverter NMOStransistor 844 to be higher relative to the resistance of transistor831. Thus, the voltage placed at the data/true side of the memory bitcell at point V_(L) 808 is 2/3V due to the voltage divider circuitformed by port NMOS transistor 831 (lower resistance) and inverter NMOStransistor 844 (higher resistance).

The 2/3V value at point V_(L) 808 is high enough to flip the state ofthe memory cell since it is high enough to activate inverter 841.Specifically, as illustrated in FIG. 8B, the 2/3V value at point V_(L)808 turns off PMOS transistor 847 and turns on NMOS transistor 848 suchthat point V_(R) 809 is pulled down to a logical “0” (ground). At thispoint, the data state of the memory cell has been changed such thattrue/data side now has a logical “1” (currently represented by 2/3V) andthe false/data-complement side now has a logical “0” (represented byground). Note that to ensure inverter 841 is activated, the circuitgeometry of inverter 841 may be adjusted to slide the transfer functionof FIG. 4 to the left.

FIG. 8C illustrates a final state that is achieved after the logical “1”write operation after word line X 810 is no longer asserted such thatport transistor 831 is turned off. As illustrated in FIG. 8C, thelogical “0” at point V_(R) 809 then turns on PMOS transistor 843 andturns off NMOS transistor 844 such that point V_(L) 808 is driven to alogical “1” (now represented by a V_(DD) voltage level). The V_(DD)voltage level may be changed by an external circuit to a higher voltagelevel such as the voltage level that is used to drive the word lines(810 and 815).

FIG. 9A illustrates a first timing diagram that illustrates how a splitword line 6T SRAM cell with a variable V_(DD) power voltage level may beused to perform either two write operations or two read operations in asingle clock cycle. The upper portion of FIG. 9A illustrates how twoconcurrent write operations may be performed. A first write operationuses word line X and bit line X and a concurrent second write operationuses word line Y and bit line Y. To ensure the success of the twosingle-ended write operations, the memory control system lowers theV_(DD) power voltage provided to the memory array. Alternatively, thememory control system may just lower the V_(DD) power voltage providedto the specific rows of the memory array that are being read.

The lower portion of FIG. 9A illustrates how two single-ended readoperations may be performed. Note that the V_(DD) power voltage shouldbe driven to the normal level during the read operations such that thepre-charge phase of the read operation does not accidentally over-writedata.

As set forth in the preceding paragraphs referencing FIGS. 8A, 8B, and8C, a single-ended write of a logical “1” data bit can be performed byreducing the V_(DD) power voltage provided to a 6T SRAM bit cell whenthe write operation is performed. Thus, reducing the V_(DD) powervoltage allows for two concurrent single-ended write operations to beperformed as illustrated in the timing diagram of FIG. 9A. However,there are several other benefits to reducing the V_(DD) power voltage toa lower voltage level (V_(low)) in a SRAM bit cell array. By providing alower V_(DD) power voltage to the memory array, the memory array willconsume less power. Furthermore, there will be less leakage currentsince the amount of leakage current is exponentially proportional to thevoltage level. The reduced power consumption will also mean that lessheat will be generated by the memory array. In integrated circuits thathave heat dissipation issues, it would be beneficial to have a memoryarray that produces less heat.

Since there are several other benefits of reducing the V_(DD) powervoltage level for a memory array then instead of lowering the V_(DD)power voltage when a write operation occurs, one may instead opt toraise the V_(DD) power voltage level only when read operations occur.Specifically, the present disclosure proposes a memory system that ispowered with the V_(DD) power voltage at a reduced voltage level formost of the time and across most of the memory. The V_(DD) voltage levelprovided to the memory array is reduced relative to the voltage levelused to activate the word lines in the array. However, when a readoperation occurs, the memory control circuitry then raises the V_(DD)voltage to a level that ensures the pre-charge operation does notaccidentally over-write the currently stored data value in a memorycell. In this manner the memory array has the advantages of reducedpower usage along with the ability to perform both single-ended readsand writes.

FIG. 9B illustrates a timing diagram that illustrates how a split wordline 6T SRAM array with a variable V_(DD) power voltage level may beused to perform either two concurrent write operations or two concurrentread operations in a single clock cycle. The memory array for the systemof FIG. 9B is generally provided with a reduced V_(DD) voltage for mostof the array and most of the time. (The V_(DD) voltage level is reducedrelative to the voltage level placed on word lines to activate porttransistors.) The reduced V_(DD) voltage allows the memory array tohandle two concurrent single-ended write operations as illustrated bythe upper portion of FIG. 9B. However, the reduced V_(DD) power voltagecould potentially cause the pre-charge during a read operation toover-write stored data. Thus, the memory system raises the V_(DD) powervoltage when performing read operations as illustrated in the lowerportion of FIG. 9B. The V_(DD) power voltage may be raised for theentire memory array during the read operations. However, a moreefficient implementation will only raise the V_(DD) power voltageprovided to the specific memory rows that are currently being read.

One Read and One Write Concurrently

The previous sections described how the 6T SRAM cell of FIG. 6A can beused to implement a memory system that handles two concurrent readoperations or two concurrent write operations in a single operatingcycle. Thus, a 2R or 2W memory system may be created using the teachingsof the previous sections. However, a true dual-port memory system shouldbe able to handle two concurrent read operations (2R), two concurrentwrite operations (2W), or one read operation and one concurrent writeoperation (1W and 1R) in a single cycle.

At first glance, it would seem easy to add the ability to perform oneindependent read operation and one independent write operation (1W and1R) in a single cycle. For example, word line X 610 and bit line X 620could be used for a read operation and word line Y 615 and bit line Y625 could be concurrently used for a write operation. This will indeedwork if the read and write operations access memory cells in rows faraway from each other. But if the read and write operations access thesame row of memory cells then the two operations cannot be performedconcurrently. Specifically, the write operation uses a low V_(DD) powervoltage while the read operation uses a high V_(DD) power voltage andsince the memory cells in the same row are served by the same V_(DD)power line, the concurrent read and write operations that use twodifferent V_(DD) power voltage levels cannot be handled concurrently.

The situation for concurrent read and write operations is actually evenmore difficult than that. FIG. 10 illustrates a conceptual block diagramfor a five cell (horizontally) by six cell (vertically) subsection of amemory array that uses split word lines. In the memory array subsectionof FIG. 10, each memory cell row is served by a pair of horizontal wordlines (W_(X) and W_(Y)) and each memory cell column is served by a pairof associated bit lines (BL_(X) and BL_(Y)). However, although each rowhas independent word lines (W_(X) and W_(Y)), each row of memory cellsin FIG. 10 shares a common V_(DD) power voltage line with an adjacentrow of memory cells. For example, all of the memory cells in row 0 sharea common V_(DD) power voltage line will all of the memory cells inrow 1. Similarly, all of the memory cells in row 2 share a common V_(DD)power voltage line will all of the memory cells in row 3. Thisarrangement is created by laying out mirror image memory cells extendingfrom the common V_(DD) power voltage line. Using a common V_(DD) powervoltage line maximizes the memory array density by reducing the numberof V_(DD) power voltage lines by one half. However, this layout areaefficient arrangement complicates a memory system that operates bydynamically adjusting the voltage level on the V_(DD) power voltageline. Specifically, if a memory write operation and a memory readoperation attempt to access the same memory row or adjacent memory rowsthat share a common V_(DD) power voltage line, then these two operationscannot be performed concurrently.

To resolve this situation wherein read operations and write operationsconflict with each other, a write buffer may be added to the memorysystem in order to handle conflicts. FIG. 11 illustrates a block diagramof a memory system 1100 that includes two write buffer rows 1141 and1142 such that memory system 1100 can handle two concurrent readoperations (2R), two concurrent write operations (2W), or one readoperation and one concurrent write operation (1W and 1R) in a singlecycle.

The write buffer rows 1141 and 1142 are the same width as the rows inthe main memory array 1150 and each column entry is associated with thematching column in the main memory array 1150. When there is a conflictbetween a read operation and write operation that attempt to access rowsserved by the same V_(DD) power voltage line then the read operation isgiven priority to access the memory array 1150 and the write operationstores the write data into the associated column entry of one of thewrite buffer rows 1141 or 1142. A write buffer mapping table 1145 isused to keep track of which data rows currently have valid data storedin the write buffer. A full description of the operation of the memorysystem 1100 is presented with reference to the flow diagrams illustratedin FIGS. 12A and 12B.

The write buffer rows 1141 and 1142 and the write buffer mapping table1145 may be implemented in a variety of different manners. For example,these memory structures may be created with physical memory circuitarrays. Alternatively, these structures may be implemented withregister-transfer level (RTL) code in a hardware design language (HDL)such that the actual memory circuits are synthesized with flip-flops orother memory circuits when the RTL code is processed by a synthesistool.

The flow diagrams of FIGS. 12A and 12B conceptually illustrate theoperation of the memory system 1100 of FIG. 11. Note that variousoperations are illustrated sequentially in FIGS. 12A and 12B for claritybut many of these stages may be performed in parallel. Referring to thetop of FIG. 12A, the memory system receives two memory access operationsat stage 1201 that may be two concurrent read operations (2R), twoconcurrent write operations (2W), or one read operation and oneconcurrent write operation (1W and 1R) in a single cycle. At stage 1205the memory system determines how to proceed depending upon what type ofmemory operations were received.

If two write operations (2W) were received, the system proceeds to stage1221 where the two data values are written into the memory array 1150 ofthe memory system 1100. There is no conflict since the memory array 1150can handle two concurrent memory write operations to any two locationswithin the memory array 1150 as set forth with reference to FIGS. 9A and9B. However, in some embodiments a write buffer may be used to handleone write operation if the write operations are directed to the same rowin order to improve memory system performance as will be described in alater section of this document.

After writing the two data values the memory controller 1110 may updatethe write buffer mapping table 1145 at stage 1225 if necessary. Forexample, if the memory system wrote a data value into the memory array1150 that was previously represented in one of the write buffer rows1141 or 1142 then the memory controller 1110 updates the write buffermapping table 1145 to indicate that the valid data is now stored withinthe memory array 1150. The system then returns back to stage 1201 tohandle the next pair of memory access requests.

Referring back to stage 1205, if two read operations (2R) were received,the system proceeds to stages 1210 and 1211 where the memory controller1110 reads the write buffer mapping table 1145 and determines where therequested data is located. If one or both of the requested data itemsare reside within the write buffer rows 1141 or 1142 then the systemproceeds to stage 1212 where the requested data is served from the writebuffer. At stage 1213, the memory system determines if both data itemswere served from the write buffer and if both items were served from thewrite buffer then the memory controller may return back to stage 1201 tohandle the next pair of memory access requests.

If stage 1211 determined that neither requested data item was in thewrite buffer or stage 1213 determined that only one data item was servedfrom the write buffer then the system proceeds to stage 1214 to handlethe remaining data requests. At stage 1214, the memory controller 1110raises the V_(DD) power voltage line for the row or rows in the memoryarray 1150 that contain the remaining data. The memory system thenserves the remaining data from the memory array 1150 at stage 1215 andthen returns back to stage 1201 to handle the next pair of memory accessrequests.

Referring back to stage 1205, if a read operation (1R) and a writeoperation (1W) were received, then the system proceeds to stage 1230 onFIG. 12B to handle the concurrent memory read and write memory requests.At stage 1230, the memory controller 1110 reads the write buffer mappingtable 1145 to determine where the data requested in the read operationis located. If stage 1231 determines that the requested data itemresides within one of the write buffer rows 1141 or 1142 then the systemproceeds to stage 1232 where the requested data item is served from thewrite buffer. The memory system can then handle the write operation atstage 1235 by writing the data into the memory array 1150. Finally, thememory controller 1110 may update the write buffer mapping table 1145 atstage 1275 if the data written into the memory array 1150 at stage 1235was previously represented in the write buffer by invalidating thatentry in the write buffer. Note that in a real system, the read from thewrite buffer and the write into the memory array 1150 will be performedin parallel. The memory system then returns back to stage 1201 to handlethe next pair of memory access requests.

Referring back to stage 1231, if the data being read was not in thewrite buffer then the memory system determines if there is a rowconflict between the read operation and the write operation at stage1240. There is a row conflict if the read operation and the writeoperation access data cells that are served by the same V_(DD) powervoltage line. As illustrated in FIG. 10, this may occur when the twodata cells are located in the same row or in adjacent rows that sharethe same V_(DD) power voltage line.

If stage 1240 determines that there is no row conflict then the memorysystem may proceed to stage 1241 to handle the non-conflicting read andwrite operations. The system handles the read operation by raising theV_(DD) power voltage line for the row containing the read data at stage1241 and serving the data from that row in the memory array 1150 atstage 1245. The system handles the write operation by writing the writedata into the memory array 1150. The memory system may need to updatethe write buffer mapping table 1145 at stage 1275 if the data writteninto the memory array 1150 was previously represented in the writebuffer by invalidating the entry in the write buffer. Note that in animplemented memory system, the non-conflicting read from and the writeinto the memory array may be performed in concurrently. The system maythen return back to stage 1201 to handle the next two memory accessrequests.

Referring back stage 1240, if there is a conflict between the readoperation and the write operation then the memory controller must usethe write buffer to handle the conflicting operations. The readoperation is given priority such that the memory controller 1110 raisesthe V_(DD) power voltage line for the row containing the read data atstage 1261 and serves the requested data from that row in the memoryarray 1150 at stage 1262. The conflicting write operation must then behandled using the write buffer in the memory system.

To handle the conflicting write operation, the memory controller 1110first determines if the associated data entry in the write bufferalready stores other valid data at stage 1270. If other valid data isalready stored in the write buffer then that data is ejected from thewrite buffer and written into the memory array 1150 at stage 1271. Then,if the write buffer entry was not already used or after the current dataentry was ejected at stage 1271, the memory system can write the newdata into the write buffer at stage 1272. Finally, at stage 1275, thememory controller updates the write buffer mapping table 1145 asrequired. If the write operation wrote into an empty data entry orreplaced an ejected data entry then the memory controller updates thewrite buffer mapping table 1145 to reflect the new data stored into thewrite buffer. If write operation over-wrote the previously valid datafor the same address then no update of the write buffer mapping table1145 may be required.

As set forth in the preceding paragraphs, a combination of variousdifferent techniques allows a 6T SRAM bit cell to be used to implement afull dual-port memory system. First, a split word line allows the twodifferent sides of a 6T SRAM bit cell to be accessed independently. Thisallows two concurrent independent read operations to be performed. Apseudo-differential read system may be used to improve the speed ofsingle-ended read operations.

Second, control of the V_(DD) power voltage line for a memory cellenables single-ended write operations to write either logical “0”s orlogical “1”s into either side of a 6T SRAM bit cell. Specifically,reducing the voltage level on the V_(DD) power voltage line relative tothe voltage level placed on the word line allows for single-ended writesof logical “1”s that were previously not possible. Thus, the techniqueof reducing the voltage level on the V_(DD) power voltage line allowstwo concurrent independent write operations to be performed.

And third, the addition of a write buffer into a memory system allowsfor one read and one write operation to be handled concurrently byresolving any possible conflict between the read operation and the writeoperation. As set forth in the previous paragraph, reducing the voltagelevel on the V_(DD) power voltage line is required to allow asingle-ended write of a logical “1” into a SRAM bit cell. However,reducing the voltage level on the V_(DD) power voltage line prevents aconcurrent read operation from any memory cells served by the sameV_(DD) power voltage line since the reads may accidentally destroy data.To resolve such conflicting read and write operations, the readoperation is given priority to access the memory array whereas the writeoperation writes into a write buffer if there is a conflict.

Write Buffer Usage in Other Dual-Port Memory Systems

The previous section described how a write buffer may be used toimplement a fully functional dual-port memory system that is constructedfrom 6T SRAM bit cells that have individually controllable word lines.However, a write buffer may also be used to improve the operation ofexisting dual-port memory systems.

FIG. 5A illustrates an 8T SRAM bit cell that may be used in aconventional dual-port memory system. When there are two differentmemory operations that access the same row of a memory array, those twodifferent operations can interfere with each other to reduceperformance. For example, if a read operation is using word line A 510,bit line A 520, and bit line A-complement 525 to read a data value fromthe memory bit cell then a concurrent write operation directed at adifferent memory cell in the same row may impede the read operation.Specifically, a concurrent write operation to a different cell in thesame row will activate word line B 511 that will turn on porttransistors 533 and 534. Thus, activating word line B 511 couples bitline B 521 and bit line B complement 526 to the memory cell such thatthe line capacitance of the SRAM bit cell is greatly increased. Theincreased line capacitance will increase the amount of time needed toread the data bit from the memory cell such that a concurrent writeoperation to the same row (but in a different column) reduces theperformance of the read operation.

When concurrent read operations and write operations access differentrows in the memory array, there is significantly less capacitanceexperienced such that read operations without concurrent writeoperations to the same row may be completed much faster. But in order toprovide reliable operation with full random access to all memory cells,the memory access speed must be limited to the worst case scenario.Thus, the memory access speed specifications are determined by the worstcase scenario of concurrent read and write operations directed to thesame row in the memory array.

The same situation may also be true for two concurrent write operationsdirected at two different memory cells within the same row. When twowrite operations access two memory cells in the same row of a memoryarray then the circuits driving the bit lines will have to deal withincreased capacitance. Specifically, for both write operations, theother write operation will couple the other pair of bit lines to memorycell by activating the other pair of port transistors. Thus both writeoperations to memory cells in the same row experience increased linecapacitance. Therefore, it may take a longer time to complete writeoperations directed to memory cells in the same row than if the twowrite operations were directed to memory cells located in differentrows. The issue is generally more of a problem for read operations sincewrite operations can use larger driver circuits that are located outsideof the memory array.

In some multi-port memory systems, a concurrent read operation and writeoperation to the same row causes the memory to operate slower than whentwo concurrent read operations to the same row are handled. (Aconcurrent read operation and write operation to the same row is theworst case situation.) To improve the performance of such a memorysystem, a write-buffer may added to handle concurrent read and writeoperations directed to the same row such that the two concurrent readoperations to the same row then becomes the worst case situation. Thus,the overall performance of the memory system is improved. FIG. 13illustrates a dual-port memory system that uses a write buffer 1340 toimprove the performance of the multi-port memory system in such amanner.

Referring to FIG. 13, a dual-port memory system 1300 is implemented withmemory controller logic 1310, a main dual-port memory array 1350, awrite buffer row 1340, and a write buffer mapping table 1345. The memorycontroller logic 1310 handles all memory requests from users of thedual-port memory system 1300. Most data items are represented in themain dual-port memory array 1350. However, some data items may berepresented in the write buffer row 1340. The memory controller logic1310 uses write buffer mapping table 1345 to keep track of which dataitems are currently represented in the write buffer row 1340 instead ofin the main dual-port memory array 1350.

To improve memory system performance with a memory array that hasreduced performance when read and write operations access the same rowconcurrently, the memory controller logic 1310 logic of dual-port memorysystem 1300 uses the write buffer row 1340 to prevent such concurrentread and write operations within the same row. FIG. 14 illustrates aflow diagram that describes how the memory controller logic 1310 handlesconcurrent read and write operations.

At stage 1401, the memory controller logic 1310 receives both a readoperation and a write operation. The memory controller logic 1310 firstreads the write buffer mapping table 1345 at stage 1403 to locate theread data. If the read data is in the write buffer row 1340 then thesystem proceeds through stage 1405 to stage 1410 where the read data isserved from the write buffer row 1340. The write operation is handled bywriting into the main dual-port memory array 1350 at stage 1425. Atstage 1426, the memory controller logic 1310 will update the writebuffer mapping table 1345 if the data written into the main dual-portmemory array 1350 at stage 1425 was previously represented in the writebuffer 1340. It must be again emphasized that operations may be listedsequentially in the flow diagrams for clarity but will generally beperformed in parallel whenever possible. For example, the read operationof stage 1410 and the write operation of stage 1425 will generally beperformed concurrently.

Referring back to stage 1405, if the read data is not in the writebuffer row 1340 then the system determines if the read and write areattempting to access the same row at stage 1430. If the read and writeoperations are not attempting to access the same row in the maindual-port memory array 1350 then the memory controller logic 1310 canjust proceed to stage 1435 and handle both the read and write operationswith the main dual-port memory array 1350 since there is no performancepenalty when the two operations do not access the same row. The systemthen proceeds through stage 1426 to update the buffer mapping table 1345if necessary. For example, if the write data was previously beenrepresented in the write buffer 1340 then the memory controller logic1310 updates the write buffer mapping table 1345 to indicate that thewrite data is now represented in the memory array 1350.

If stage 1430 determines that the read and write operations are bothattempting to access the same row in the main dual-port memory array1350 then the memory controller logic 1310 uses the write buffer 1340 toprevent both operations from accessing the same row concurrently. Theread operation is given priority since the read data only exists withinthe main dual-port memory array 1350 such that the read operation ishandled by serving the data from the main dual-port memory array 1350 atstage 1440. The write operation is directed to the write buffer row1340.

At stage 1450, the system determines if the associated entry in thewrite buffer row 1340 is already being used by different data address(from a different row). If the associated entry current contains validdata from a different data address, that data is ejected from the writebuffer row 1340 and written into the main dual-port memory array 1350 atstage 1451. (Note that this write operation can be performedconcurrently with the read from a different row at stage 1440 since themain array is a dual-port memory array.) After ejecting the data atstage 1451 or if the data entry did not store a different data addressback at stage 1450, the memory controller logic 1310 writes the writedata into the write buffer row 1340 at stage 1452. Finally, at stage1426 the memory controller logic 1310 updates the write buffer mappingtable 1345 to indicate the new data stored in the associated entry ofthe write buffer row 1340 if previously stored data was rejected atstage 1451.

The performance of a dual port memory may be limited by many differentcases. As set for the in the previous paragraphs, 2W or 1R1W operationscould limit the performance to a lower operating frequency, as comparedto the 2R case. For example, a memory system may be able to operate at aclock frequency of 1.3 GHz for the 2R case, but only be able to operateat a clock frequency of 1 GHz when 2W or 1R1W operations occur due tothe slow down when the operations access the to the same or adjacentrows. Thus, using the technique set forth in the previous paragraphswill eliminate the performance bottleneck from the 2W and 1R1Woperations case and thereby allow the dual port memory system to operateat a clock frequency of 1.3 GHz at all times.

High-Speed 1R1W Two-Port Memory System from Dual-Port Memory

In the previous section, the techniques set forth with reference toFIGS. 13 and 14 improve the performance of 1 R1W operations and 2Woperations that access the same row. However, two read operations (2R)that access the same row in a memory array cannot be improved with awrite buffer since read data can only be obtained from where the validread data resides. Thus, if a write buffer is used to improve theperformance of 1R1W and 2W operations to the same row then two readoperations (2R) may become the worst case scenario that limits theperformance of a dual-port memory system.

However, many memory applications do not require dual-port memorysystems that have two completely independent memory ports but caninstead operate with a two-port memory system wherein one port onlyhandles read operations and the other port only handles writeoperations. Thus, if one uses the techniques set forth with reference toFIGS. 13 and 14 improve the performance of 1R1W operations of a dualport memory system and labels the memory system as a 1R1W two-portmemory system, a dual port memory system may be used to construct ahigh-speed 1R1W two-port memory system.

When a dual-port memory system is used as a 1R1W two-port memory system,the performance of the memory system is limited only by the speed atwhich 1R1W operations can be done (2R and 2W operations will not beperformed). If the dual-port memory system can handle 1R1W operations todifferent rows at a clock frequency of 1.3 GHz but can only handle 1R1Woperations to the same/adjacent row at a clock frequency of 1 GHz thenthe techniques from the previous section may be used to improve the 1R1Wperformance of the two-port memory system. Specifically, a write buffermay be added to handle write operations when the write operation isdirected at the same row as the read operation. In this manner, the 1R1Wtwo-port memory system can always operate at the full 1.3 GHz clockrate. Thus, a high performance 1R1W two-port memory system comprisingone read port and one write port may be constructed from a dual-portmemory system that includes a write buffer.

The preceding technical disclosure is intended to be illustrative, andnot restrictive. For example, the above-described embodiments (or one ormore aspects thereof) may be used in combination with each other. Otherembodiments will be apparent to those of skill in the art upon reviewingthe above description. The scope of the claims should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled. In the appendedclaims, the terms “including” and “in which” are used as theplain-English equivalents of the respective terms “comprising” and“wherein.” Also, in the following claims, the terms “including” and“comprising” are open-ended, that is, a system, device, article, orprocess that includes elements in addition to those listed after such aterm in a claim is still deemed to fall within the scope of that claim.Moreover, in the following claims, the terms “first,” “second,” and“third,” etc. are used merely as labels, and are not intended to imposenumerical requirements on their objects.

The Abstract is provided to comply with 37 C.F.R. §1.72(b), whichrequires that it allow the reader to quickly ascertain the nature of thetechnical disclosure. The abstract is submitted with the understandingthat it will not be used to interpret or limit the scope or meaning ofthe claims. Also, in the above Detailed Description, various featuresmay be grouped together to streamline the disclosure. This should not beinterpreted as intending that an unclaimed disclosed feature isessential to any claim. Rather, inventive subject matter may lie in lessthan all features of a particular disclosed embodiment. Thus, thefollowing claims are hereby incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment.

1. A dual-port random access memory system, said dual-port random accessmemory system comprising: a memory array, said memory array comprising aplurality of memory cells, each of said memory cells comprising a memoryelement, said memory element having a true side and a false side, afirst bidirectional memory port, said first bidirectional memory portcoupled to said true side, said first bidirectional memory portcontrolled by a first word line, said first bidirectional memory portcoupled to a first bit line, a second bidirectional memory port, saidsecond bidirectional memory port coupled to said false side, said secondbidirectional memory port controlled by a second word line, said secondmemory port coupled to a second bit line, and a power line for providingelectrical voltage to the memory cell; and a memory array controller,said memory array controller driving said power line at a first voltagelevel lower than a normal second voltage level provided on said firstword line when performing a write operation to said first bidirectionalmemory port, said memory array controller driving said power line atsaid first voltage level lower than said normal second voltage levelprovided on said second word line when performing a write operation tosaid second bidirectional memory port wherein said memory system handlestwo write operations in a single clock cycle by directing a first writeoperation to said first bit line and a second write operation to saidsecond bit line during said single clock cycle.
 2. The dual-port randomaccess memory system as set forth in claim 1 wherein said memory elementcomprises a pair of inverters.
 3. The dual-port random access memorysystem as set forth in claim 1 wherein each of said memory cellscomprises a total of six transistors.
 4. The dual-port random accessmemory system as set forth in claim 1 further comprising: a voltagereference generation circuit, and a sense amplifier, said senseamplifier coupled to said voltage reference circuit and said first bitline; wherein a pseudo differential read operation may be performed byhaving said sense amplifier compare a data value on said first bit linewith a reference voltage value generated by said voltage referencecircuit.
 5. The dual-port random access memory system as set forth inclaim 1 wherein said memory array controller holds said power line atsaid first voltage level when not performing an operation.
 6. Thedual-port random access memory system as set forth in claim 1 whereinsaid memory array controller raises said power line to said secondnormal voltage level when performing a read operation on said memorycell.
 7. A method of performing two single-ended memory cell operationsin a memory system during a single clock cycle, said method comprising:receiving a first write operation to write a first data bit in a firstmemory cell circuit in a first row of a memory array; receiving a secondwrite operation to write a second data bit in a second memory cellcircuit in a second row of a memory array; and during said single clockcycle, performing the operations of driving a first word line of saidfirst row of said memory array at a first voltage level to activate afirst transistor in said first memory cell circuit, driving a firstvoltage supply provided to said first row of said memory array at asecond voltage level that is lower than said first voltage level toincrease a resistance of a second transistor in said first memory cellcircuit, driving said first data bit through said first transistorcoupled to said second transistor in said first memory cell circuit towrite said first data bit into said first memory cell circuit, driving asecond word line of said first second of said memory array at said firstvoltage level to activate a third transistor in said second memory cellcircuit, driving a second voltage supply provided to said second row ofsaid memory array at said second voltage level that is lower than saidfirst voltage level to increase a resistance of a fourth transistor insaid second memory cell circuit, driving said second data bit throughsaid third transistor coupled to said fourth transistor in said secondmemory cell circuit to write said second data bit into said secondmemory cell circuit.
 8. The method of performing two single-ended memorycell operations during a single clock cycle as set forth in claim 7wherein said first memory cell circuit comprises a pair of inverters. 9.The method of performing two single-ended memory cell operations duringa single clock cycle as set forth in claim 7 wherein said first memorycell circuit comprises a six transistor SRAM cell circuit. 10.(canceled)
 11. The method of performing two single-ended memory celloperations during a single clock cycle as set forth in claim 7, saidmethod further comprising: holding said first voltage supply at saidsecond voltage level when not performing an operation.
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